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functional block diagrams general description the ssm2018t and ssm2118t represent continuing evolu- tion of the frey operational voltage controlled element (ovce) topology that permits flexibility in the design of high performance volume control systems. voltage (ssm2018t) and differential current (ssm2118t) output versions are of- fered, both laser-trimmed for gain core symmetry and offset. as a result, the ssm2018t is the first professional audio quality vca to offer trimless operation. the ssm2118t is ideal for low noise summing in large vca based systems. due to careful gain core layout, the ssm2018t/ssm2118t combine the low noise of class ab topologies with the low dis- tortion of class a circuits to offer an unprecedented level of sonic transparency. additional features include differential in- puts, a 140 db gain range, and a high impedance control port. the ssm2018t provides an internal current-to-voltage con- verter; thus no external active components are required. the ssm2118t has fully differential current outputs that permit high noise-immunity summing of multiple channels. both devices are offered in 16-pin plastic dip and soic pack- ages and guaranteed for operation over the extended industrial temperature range of C40 c to +85 c. * protected by u.s. patent nos. 4,471,320 and 4,560,947. features 117 db dynamic range 0.006% typical thd+n (@ 1 khz, unity gain) 140 db gain range no external trimming required differential inputs complementary gain outputs buffered control port iCv converter on-chip (ssm2018t) differential current outputs (ssm2118t) low external parts count low cost trimless voltage controlled amplifiers ssm2018t/ssm2118t* information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 rev. a a v c ?n +in v g v 1? ? g ? 1? gain core g 1? ssm-2018t v c ?n +in +i g v 1? ? g ? 1? gain core g 1? ssm-2118t
rev. a C2C ssm1018t/ssm2118tCspecifications electrical specifications parameter conditions min typ max units audio performance 1 noise v in = gnd, 20 khz bandwidth C95 C93 dbu headroom clip point = 1% thd+n +22 dbu total harmonic distortion plus noise 2nd and 3rd harmonics only (+25 c to +85 c) a v = 0 db, v in = +10 dbu 0.006 0.025 % a v = +20 db, v in = C10 dbu 0.013 0.04 % a v = C20 db, v in = +10 dbu 2 0.013 0.04 % input amplifier bias current v cm = 0 v 0.25 1 m a offset voltage v cm = 0 v 1 15 mv offset current v cm = 0 v 10 100 na input impedance 4m w common-mode range 13 v gain bandwidth vca configuration 0.7 mhz vcp configuration 14 mhz slew rate 5v/ m s output amplifier (ssm2018t) offset voltage v in = 0 v, v c = +4 v 1.0 15 mv output voltage swing i out = 1.5 ma positive +10 +13 v negative C10 C14 v minimum load resistance for full output swing 9 k w control port bias current 0.36 1 m a input impedance 1m w gain constant device powered in socket > 60 sec C30 mv/db gain constant temperature coefficient C3500 ppm/ c control feedthrough 0 db to C40 db gain range 1 4mv maximum attenuation v c = +4 v 100 db power supplies supply voltage range 5 18 v supply current 11 15 ma power supply rejection ratio 80 db notes 1 ssm2118t tested and characterized using op275 as current-to-voltage converter, see figure next page. 2 guaranteed by characterization data and testing at a v = 0 db. specifications subject to change without notice. [v s = 15 v, a v = 0 db, r l = 100 k w , f = 1 khz, 0 dbu = 0.775 v rms, simple vca application circuit with 18 k w resistors, Cv in floating, and class ab gain core bias (r b = 150 k w ), C40 c < t a < +85 c, unless otherwise noted. typical specifications apply at t a = +25 c.]
rev. a C3C ssm2018t/ssm2118t absolute maximum ratings 1 supply voltage dual supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s operating temperature range . . . . . . . . . . . . . C40 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . . +300 c thermal characteristics thermal resistance 2 16-pin plastic dip q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 c/w 16-pin soic q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 c/w transistor count number of transistors ssm2018t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ssm2118t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 esd ratings 883 (human body) model . . . . . . . . . . . . . . . . . . . . . . . 500 v eiaj model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 v 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. 2 q ja is specified for worst-case conditions, i.e., q ja is specified for device in socket for p-dip and device soldered in circuit board for soic package. ordering guide model temperature range package option* SSM2018TP C40 c to +85 c n-16 ssm2018ts C40 c to +85 c r-16 ssm2118tp C40 c to +85 c n-16 ssm2118ts C40 c to +85 c r-16 *n = plastic dip; r = sol. pin configurations 16-lead plastic dip and sol 16-lead plastic dip and sol +i 1? v+ bal comp 1 +in ?n mode v c v ? 1? ? g v g gnd comp 2 comp 3 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) ssm2018t v 1? +i 1? v+ bal comp 1 +in ?n mode v c v ? 1? gnd comp 2 comp 3 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) ssm2118t v 1? ? g +i g ssm2018t typical application circuit ssm2118t typical application circuit 1 m f 18k v in+ v 150k a1 10k 10k 18k 18k 500k 50pf v out global symmetry trim from additional ssm2118ts v 1 m f 18k v in 47pf 1 m f 3k v control v+ 50pf * 470k optional trim 47k 47k a1, a2: op275 1 2 5 6 7 3 4 8 16 15 12 11 10 14 13 9 ssm2118t a2 1k * for more than 2 ssm2118ts warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ssm2018t/ssm2118t features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. v+ 1 m f 150k 18k v+ 18k v in+ 1 m f 18k v in 47pf 1 m f 50pf 1k v control 3k v out v 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 ssm2018t
C4C ssm2018t/ssm2118tCtypical characteristics rev. a 0.1 0.010 0.001 thd + n ?% 20 100 1k 10k 20k frequency ?hz av = +20db av = ?0db av = 0db t a = +25 c v s = 15v r f = 18k w figure 1. ssm2018t thd + n frequency (80 khz low-pass filter, for a v = 0 db, v in = 3 v rms; for a v = +20 db, v in = 0.3 v rms; for a v = C20 db, v in = 3 v rms) 100 0 0.025 30 10 20 0.000 60 40 50 70 80 90 0.020 0.015 0.010 0.005 distortion ?% units t a = +25 c a v = 0db 300 units v in = 10dbu v s = 15v figure 2. ssm2018t distortion distribution 1 0.1 0.010 0.001 thd + n ?% 0.1 11020 amplitude ?v rms t a = +25 c r f = 18k w v s = 15v figure 3. ssm2018t thd + n vs. amplitude (gain = 0 db, f in = 1 khz, 80 khz low-pass filter) 1 0.1 0.010 0.001 thd + n ?% 10m 0.1 1 2 amplitude ?v rms t a = +25 c v s = 15v r f = 18k w figure 4. ssm2018t thd + n vs. amplitude (gain = +20 db, f in =1 khz, 80 khz low-pass filter) 1.0 0.01 0.001 ?0 ?0 20 ?0 0.1 040 t a = +25 c v s = 15v r f = 18k w gain ?db thd + n ?% figure 5. ssm2018t thd + n vs. gain (f in = 1 khz; for C60 db a v C20 db, v in = 10 v rms; for 0 db a v +20 db, v in = 1 v rms) thd + n ?% 0.1 0.001 0 12 0.01 t a = +25 c r f = 18k w 3 6 9 15 18 supply voltage ?volts figure 6. ssm2018t thd + n vs. supply voltage (a v = 0 db, v in = 1 v rms, f in = 1 khz, 80 khz low-pass filter)
rev. a C5C ssm2018t/ssm2118t load resistance ? w maximum output swing ?v peak 15 12 0 100 1k 100k 10k 9 6 3 r f = 18k w t a = +25 c v s = 15v figure 10. ssm2018t maximum output swing vs. load resistance, (thd = 1 % max) 100 0 40 30 10 ?0 20 ?0 60 40 50 70 80 90 20 0 ?0 ?0 t a = +25 c v s = 15v gain ?db output offset ?mv figure 11. ssm2018t output offset vs. gain +10 0 ?5 1k 1m 100k 10k 100 ? ?0 +5 frequency ?hz t a = +25 c v s = 15v gain ?db 0 ?35 ?5 ?0 phase ?degrees gain phase figure 12. ssm2018t gain/phase vs. frequency figure 7. ssm2018t noise density vs. frequency 0 15 5 5 10 0 20 20 15 10 supply voltage ?volts output voltage swing ?v peak r l = w r l = 10k w r f = 18k w t a = +25 c figure 8. ssm2018t maximum output swing vs. supply voltage (thd = 1% max) frequency ?hz maximum output swing ?v peak r l = r l = 10k r f = 18k w t a = +25 c v s = 15v 9 0 1k 10k 100k 3 6 12 15 figure 9. ssm2018t maximum output swing vs. frequency (thd = 1 % max) 500 300 0 100 100k 10k 1k 10 200 100 400 frequency ?hz noise density ?nv/ ? hz t a = +25 c v s = 15v
rev. a C6C ssm2018t/ssm2118tCtypical characteristics 60 40 ?0 100 1k 10m 1m 100k 10k 20 0 ?0 ?0 ?0 frequency ?hz t a = +25 c v s = 15v gain ?db figure 13. ssm2018t gain vs. frequency thd + n ?% 0.1 0.010 0.001 20 100 1k 10k 20k frequency ?hz t a = +25 c r f = 18k w a v = 0db a v = +20db a v = ?0db figure 14. ssm2118t thd + n frequency (80 khz low-pass filter, for a v = 0 db, v in = 1 v rms; for a v = +20 db, v in = 0.1 v rms; for a v = C20 db, v in = 10 v rms) 100 0 0.025 30 10 20 0.000 60 40 50 70 80 90 0.020 0.015 0.010 0.005 distortion ?% units t a = +25 c a v = 0db 300 units v in = 10dbu v s = 15v figure 15. ssm2118t distortion distribution amplitude ?v rms t a = +25 c v s = 15v 0.1 1 10 20 1 0.1 0.010 0.001 thd + n ?% figure 16. ssm2118t thd + n vs. amplitude (gain = 0 db, f in = 1 khz, 80 khz low-pass filter) amplitude ?v rms t a = +25 c v s = 15v 10m 0.1 1 2 1 0.1 0.010 0.001 thd + n ?% figure 17. ssm2118t thd + n vs. amplitude (gain = +20 db, f in = 1 khz, 80 khz low-pass filter) 1.0 0.001 ?0 ?0 ?0 0 +20 +40 0.1 0.01 gain ?db thd + n ?% t a = +25 c v s = 15v figure 18. ssm2118t thd + n vs. gain (f in = 1 khz; for C60 db a v C20 db, v in = 10 v rms; for 0 db a v +20 db, v in = 1 v rms)
rev. a C7C ssm2018t/ssm2118t supply voltage ?volts thd + n ?% t a = +25 c 0.1 0.01 0.001 0 3 6 9 12 15 18 figure 19. ssm2118t thd + n vs. supply voltage (a v = 0 db, v in = 1 v rms, f in = 1 khz, 80 khz low-pass filter) figure 20. ssm2118t noise density vs. frequency 0 15 5 10 0 5 10 15 20 20 supply voltage ?volts output voltage swing ?v peak r l = w 20 t a = +25 c figure 21. ssm2118t maximum output swing vs. supply voltage (thd = 1% max) 9 0 1k 10k 100k 3 6 12 15 frequency ?hz maximum output swing ?v peak t a = +25 c v s = 15v figure 22. ssm2118t maximum output swing vs. frequency (thd = 1 % max) 10 0 40 3 1 ?0 2 ?0 6 4 5 7 8 9 20 0 ?0 ?0 gain ?db output offset current ?? t a = +25 c v s = 15v figure 23. ssm2118t output offset current vs. gain +10 0 ?5 1k 1m 100k 10k 100 ? ?0 +5 frequency ?hz gain ?db 0 ?35 ?5 ?0 phase ?degrees t a = +25 c v s = 15v phase gain figure 24. ssm2118t gain/phase vs. frequency 500 300 0 10 100 1k 10k 100k 200 100 400 t a = +25 c v s = 15v frequency ?hz noise density ?nv/ ? hz
rev. a C8C ssm2018t/ssm2118t 60 40 ?0 100 1k 10m 1m 100k 10k 20 0 ?0 ?0 ?0 frequency ?hz gain ?db t a = +25 c v s = 1.5v op275 as i/v conv. figure 25. ssm2118t gain vs. frequency 0.06 0 100 0.03 0.01 ?0 0.02 ?0 0.05 0.04 80 40 20 060 temperature ? c distortion ?% t a = +25 c v s = 15v v in = 10dbu a v = ?0db and v in = ?0dbu a v = 20db v in = 10dbu a v = 0db figure 26. ssm2018t and ssm2118t distortion vs. temperature ?0 ?10 40 ?0 ?00 ?0 ?0 ?0 ?0 20 0 ?0 gain ?db output noise ?dbu t a = +25 c v s = 15v figure 27. ssm2018t and ssm2118t output noise vs. gain (v in = gnd, 20 khz bandwidth) 100 0 30 10 20 60 40 50 70 80 90 units control feedthrough ?mv t a = +25 c 0v < v c < 1.2v freq = 0hz 300 units ?.0 ?.0 ?.0 0 1.0 2.0 figure 28. ssm2018t control feedthrough distribution 0 ?0 ?00 100 1k 100k 10k ?0 ?0 ?0 frequency ?hz v s = 15v t a = +25 c v c = 100mv rms control feedthrough ?db figure 29. ssm2018t and ssm2118t control feedthrough vs. frequency 3 ? 100 0 ? ?0 ? ?0 2 1 80 40 20 060 temperature ? c control feedthrough ?mv v s = 15v 0v < v c < 1.2v freq = 0hz figure 30. ssm2018t and ssm2118t control feedthrough vs. temperature
rev. a C9C ssm2018t/ssm2118t ?0 ?0 ?0 100 ?5 ?5 ?0 ?0 60 80 40 20 0 temperature ? c gain constant ?mv/db v s = 15v figure 31. ssm2018t and ssm2118t gain constant vs. temperature ?8 ?3 60 ?0 ?2 ?0 ?1 ?0 ?9 40 20 0 ?0 ?0 gain ?db gain constant ?mv/db t a = +25 c v s = 15v figure 32. ssm2018t and ssm2118t gain constant linearity vs. gain 0.1 0.0 ?.4 100 1k 100k 10k ?.1 ?.2 ?.3 frequency ?hz gain ?db t a = +25 c v s = 15v a v = 0db v in = 100v rms figure 33. ssm2018t and ssm2118t gain flatness vs. frequency 0 ?0 ?00 100 100k 10k 1k 10 ?0 ?0 ?0 frequency ?hz cmrr ?db v s = 15v t a = +25 c figure 34. ssm2018t and ssm2118t cmrr vs. frequency t a = +25 c 15.0 0 15 7.5 2.5 5 5.0 0 12.5 10.0 10 supply voltage ?volts slew rate ?v/? + slew rate ?slew rate figure 35. ssm2018t and ssm2118t slew rate vs. supply voltage 0 ?0 ?00 100 100k 10k 1k 10 ?0 ?0 ?0 frequency ?hz + psrr ?psrr v s = 15v t a = +25 c psrr ?db figure 36. ssm2018t and ssm2118t psrr vs. frequency
rev. a C10C ssm2018t/ssm2118t to run it in the noninverting single-ended mode. if either input is unused, the associated 18 k w resistor and coupling capacitor should be removed to prevent any additional noise. the common-mode rejection in balanced mode is typically 55 db up to 1 khz, decreasing at higher frequencies as shown in figure 34. to ensure good cmrr in the balanced configura- tion, the input resistors must be balanced. for example, a 1% mismatch results in a cmrr of 40 db. to achieve 55 db, these resistors should have an absolute tolerance match of 0.1%. the output of the basic vca is taken from pin 14, which is the output of an internal amplifier. notice that the second voltage output (pin 16) is connected to the negative supply. this is normal and actually disables that output amplifier ensuring that it will not oscillate and cause interference problems. shorting the output to the negative supply does not cause the supply cur- rent to increase. this amplifier is only used in the ovce ap- plication explained later. the control port follows a 30 mv/db control law. the applica- tion circuit shows a 3 k w and 1 k w resistor divider from a con- trol voltage. the choice of these resistors is arbitrary and could be any values to properly scale the control voltage. in fact, these resistors could be omitted if the control voltage is already prop- erly scaled. the 1 m f capacitor is in place to provide some fil- tering of the control signal. although the control feedthrough is trimmed at the factory, the feedthrough increases with fre- quency (figure 29). thus, high frequency noise can feedthrough and add to the noise of the vca. filtering the control signal helps minimize this source of noise. theory of operation of the ssm2018t the ssm2018t has the same internal circuitry as the original ssm2018. the detailed diagram in figure 38 shows the main components of the vca. the essence of the ssm2018t is the gain core, which is comprised of two differential pairs (q1Cq4). when the control voltage, v c , is adjusted, current through the gain core is steered to one side or the other of the two differen- tial pairs. the tail current for these differential pairs is set by the mode bias of the vca (class a or ab), which is labeled as i m in the diagram. i m is then modulated by a current propor- tional to the input voltage, labeled i s . for a positive input volt- age, more current is steered (by the splitter) to the left differential pair, and the opposite is true for a negative input. to understand how the gain control works, a simple example is best. take the case of a positive control voltage on pin 11. no- tice that the bases of q2 and q3 are connected to ground via a 200 w resistor. a positive control voltage produces a positive voltage on the bases of q1 and q4. concentrating on the left most differential pair, this raises the base voltage of q1 above that of q2. thus, more of the tail current is steered through q1 than through q2. the current from the collector of q2 flows through the external 18 k w feedback resistor around amplifier a3. when this current is reduced, the output voltage is also re- duced. thus, a positive control voltage results in an attenuation of the input signal, which explains why the gain constant is negative. the collector currents of q2 and q3 produce the output volt- age. the output of q3 is mirrored by amplifier a1 to add to the overall output voltage. on the other hand, the collector cur- rents of q1 and q4 are used for feedback to the differential in- puts. because pins 6 and 4 are shorted together, any input voltage produces an input current which flows into pin 4. the applications the ssm2018t is a trimless voltage controlled amplifier (vca) for volume control in audio systems. the ssm2018t is identical to the original ssm2018 in functionality and pinout; however, it is the first professional quality audio vca in the marketplace that does not require an external trim- ming potentiometer to minimize distortion. instead, the ssm2018t is laser trimmed before it is packaged to ensure the specified thd and control feedthrough performance. this has a significant savings in not only the cost of external trimming potentiometers, but also the manufacturing cost of performing the trimming during production. the ssm2118t is identical to the ssm2018t except that dif- ferential current outputs are provided as opposed to a voltage output. this output configuration is ideal for bus summing ap- plications where multiple audio signals are summed together. these signals often require long lead lengths or cable runs to reach the summing stage. transmitting the signals in a differen- tial current mode minimizes the chance for noise pickup and for line impedances to upset the balance of the system. the ssm2118t is also factory trimmed to minimize distortion and control feedthrough. thus, no individual trim is required for each part. one global trim at the summing amplifier stage may be necessary to properly balance the resistors in this stage, as ex- plained later. basic vca configuration the primary application circuit for the ssm2018t is the basic vca configuration, which is shown in figure 37. this configu- ration uses differential current feedback to realize the vca. a complete description of the internal circuitry of the vca and this configuration is given in the theory of operation section below. the ssm2018t and ssm2118t are trimmed at the factory for operation in the basic vca configuration with class ab biasing . thus, for optimal distortion and control feedthrough perfor- mance, the same configuration and biasing should be used. all of the graphs for the ssm2018t in the data sheet have been measured using the circuit of figure 37. v+ 1 m f r b 150k 18k v+ 18k v in+ 1 m f 18k v in 47pf 1 m f 50pf 1k v control 3k v out v 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 ssm2018t figure 37. ssm2018t basic vca application circuit in the simple vca configuration, the ssm2018t inputs are at a virtual ground. thus, 18 k w resistors are required to convert the input voltages to input currents. the schematic also shows ac coupling capacitors. these are inserted to minimize dc off- sets generated by bias current through the resistors. without the capacitors, the dc offset due to the input bias current is typically 5 mv. the input stage has the flexibility to run either inverting, noninverting, or balanced. the most common configuration is
rev. a C11C ssm2018t/ssm2118t same is true for the inverting input, which is connected to pin 1. the overall feedback ensures that the current flowing through the input resistors is balanced by the collector currents in q1 and q4. basic vca configuration for the ssm2118t the ssm2118t behaves very much in the same way as the ssm2018t except that it has differential current outputs in- stead of a voltage output. the basic vca configuration is shown in figure 39. a dual output amplifier is needed to re- place the internal amplifiers in the ssm2018t. however, mul- tiple ssm2118ts can share the output amplifiers. the op amps are configured so that the ssm2118ts output current is flow- ing into a virtual ground. this same virtual ground is presented to all the vcas, allowing their currents to be summed without interaction. 1 m f 18k v in+ v 150k a1 10k 10k 18k 18k 500k 50pf v out global symmetry trim from additional ssm2118ts v 1 m f 18k v in 47pf 1 m f 3k v control v+ 50pf * 470k optional trim 47k 47k a1, a2: op275 1 2 5 6 7 3 4 8 16 15 12 11 10 14 13 9 ssm2118t a2 1k * for more than 2 ssm2118ts figure 39. ssm2118t typical bus summing application a global symmetry trim may be necessary, but since it is at the output amplifiers, only one trim is needed for any number of ssm2118ts connected to the summing bus. this trim bal- ances the resistors around the two amplifiers. if precision, matched resistors are used, the trim can be removed. however, to achieve 0.006% distortion, these resistors need to be matched to approximately 0.01%. if the choice is made to perform the trim, then one of two meth- ods may be used. the first method minimizes the distortion of an audio signal with the ssm2118t in the circuit. to perform the trim, a 0 dbu, 1 khz sine wave is applied to one of the vcas, and the output distortion is monitored. as the symmetry trim is adjusted, the output distortion will vary. the optimal adjustment produces the lowest distortion over the entire trim range. the second method is to insert a common mode signal by connecting two 47 k w resistors (matched to 0.01%) to the inverting inputs of each amplifier, as shown in the figure 39. the signal is typically a 0 dbu, 1 khz sine wave, although other signals can be used. the output is monitored with an oscillo- scope, and the potentiometer is adjusted to achieve a minimum output signal. the ssm2118t has the exact same input and gain core con- struction as the ssm2018t. thus, any discussion of these por- tions of the ssm2018t apply equally to the ssm2118t. the main difference, which is apparent by comparing figure 40 to figure 38, is the removal of two output amplifiers, a1 and a3. instead, the output currents come directly from the collectors of q2 and q3. notice that the two external amplifiers in figure 39 are configured the same as the internal amplifiers in the ssm2018t. two important characteristics of these current outputs must be considered: the output compliance and the effects of capacitive loading. normally, the outputs are connected to a virtual ground node at the summing stage, which is biased at ground. this bias point can be altered somewhat. the part maintains good distortion performance for an output compliance from a4 q3 q4 q1 q2 200 1? g g 1? 200 1.8k gain core 14 8 5 2 comp 1 compensation network 9 v ref im splitter a1 a3 v g +i 1-g 3 1 15 4 16 11 13 12 bal ? 1-g v 1-g v c gnd mode ? g comp 3 comp 2 v+ 7 6 10 v +in ?n im+( is ) 2 im? is ) 2 a2 a4 figure 38. ssm2018t detailed functional diagram
rev. a C12C ssm2018t/ssm2118t a2 a4 q3 q4 q1 q2 200 1? g g 1? 200 1.8k gain core 14 8 5 16 comp 2 comp 1 9 v ref im splitter +i g 3 1 15 4 2 11 13 12 bal ? 1? v 1? v c gnd mode ? g comp 3 7 6 10 v +in ?n +i 1? v+ compensation network im? is ) 2 im+( is ) 2 a4 C0.1 v to +6.0 v. the negative compliance is much smaller be- cause the gain core transistors (q1 and q3) begin to saturate when the collector potential is brought below their base poten- tial. these outputs have high immunity to capacitive loads. in fact, the load on either or both outputs can be as large as 10 nf with no change in the distortion performance. for values above 10 nf, the distortion does start to increase. for example, a 100 nf load causes the distortion to increase from 0.006% to 0.02% at 1 khz. the noise performance of a single ssm2118t with an op275 output amplifier is shown in figure 20. when multiple ssm2118t parts are operated in parallel, the noise does in- crease by a factor equal to the square root of the number of parts paralleled. for example, if five parts are in parallel, the total output noise is 100 nv ? (hz) ? 5 = 220 nv/ ? hz . compensating the ssm2018t and ssm2118t both parts employ the same compensation network. this net- work uses an adaptive compensation scheme that adjusts the op- timum compensation level for a given gain. the control voltage not only adjusts the gain core steering, it also adjusts the com- pensation. the ssm2018t and ssm2118t have three com- pensation pins: comp1, comp2, and comp3. comp3 is normally left open. grounding this pin actually defeats the adaptive compensation circuitry, giving the vca a fixed com- pensation point. the only time that this is desirable is when the vca has fixed feedback, such as the voltage controlled panner (vcp) circuit shown later in the data sheet. thus, for the basic vca circuit or the ovce circuit, comp3 should be left open. a compensation capacitor does need to be added between comp1 and comp2. because the vca operates over such a wide gain range, ideally the compensation should be optimized for each gain. when the vca is in high attenuation, there is very little loop gain, and the part needs to have high compen- sation. on the other hand, at high gain, the same compensation capacitor would overcompensate the part and roll off the high frequency performance. thus, the ssm2018t and ssm2118t employ a patented adaptive compensation circuit. the compen- sation capacitor is miller connected between the base and col- lector of an internal transistor. by changing the gain of this transistor via the control voltage, the compensation is changed. increasing the compensation capacitor causes the frequency re- sponse and slew rate to decrease, which will tend to cause high frequency distortion to increase. for the basic vca circuit, 47 pf was chosen as the optimal value. the ovce circuit de- scribed later uses a 220 pf capacitor. the reason for the in- crease is to compensate for the extra phase shift from the additional output amplifier used in the ovce configuration. the compensation capacitor can be adjusted over a practical range from 47 pf to 220 pf, if desired. below 47 pf, the parts may oscillate, and above 220 pf the frequency response is sig- nificantly degraded. control section as mentioned before, the control voltage on pin 11 steers the current through the gain core transistors to set the gain. the output gain formula is as follows: v out = v in e ( av c ) the exponential term arises from the standard ebers-moll equation describing the relationship of a transistors collector current as a function of the base-emitter voltage: i c = i s e ( v be / v t ) . the factor a is a function of not only v t but also the scaling due to the resistor divider of the 200 w and 1.8 k w resistors shown in figures 38 and 40. the resulting expression for a is as follows: a = 1/(10 v t ) which is approximately equal to four at room temperature. substituting a = 4 in the above equation results in a C28.8 mv/db control law at room temperature. the C28.8 mv/db number is slightly different from the data sheet specification of C30 mv/db. the difference arises from the temperature dependency of the control law. the term v t is known as the thermal voltage, and it has a direct dependency figure 40. ssm2118t detailed functional diagram
rev. a C13C ssm2018t/ssm2118t on temperature: v t = kt/q (k = boltzmanns constant = 1.38e-23, q = electron charge = 1.6e-19, and t = absolute temperature in kelvin). this temperature dependency leads to the C3500 ppm/ c drift of the control law. it also means that the control law changes as the part warms up. thus, our speci- fication for the control law states that the part has been powered up for 60 seconds. when the part is initially turned on, the temperature of the die is still at the ambient temperature (25 c for example), but the power dissipation causes the die to warm up. with 15 v sup- plies and a supply current of 11 ma, 330 mw is dissipated. this number is multiplied by q ja to determine the rise in the dies temperature. in this case, the die increases from 25 c to approximately 50 c. a 25 c temperature change causes a 8.25% increase in the gain constant, resulting in a gain constant of 30 mv/db. the graph in figure 31 shows how the gain con- stant varies over the full temperature range. proper operating mode for the ssm2018t and ssm2118t both parts have the flexibility of operating in either class a or class ab. this is accomplished by adjusting the amount of cur- rent flowing in the gain core (i m in figure 38). the traditional trade-off between the two classes is that class a tends to have lower thd but higher noise than class ab. however, by utiliz- ing well matched gain core transistors, distortion compensation circuitry, and laser trimming, the ssm2018t and ssm2118t have excellent thd performance in class ab. thus, the parts offer the best of both worlds in having the low noise of class ab with low thd. because the parts operate optimally in class ab, the distortion trim is performed for this class. to guarantee conformance to the data sheet thd specifications, both the ssm2018t and ssm2118t must be operated in class ab . this does not mean that the parts cannot be operated in class a, but the optimal thd trim point is different for the two classes. using class a operation results in a shift of thd performance from a typical value of 0.006% to 0.05% without trim. an external potentiometer could be added to change the trim back to its optimal point as shown in the ovce application circuit, but this adds the expense and time in adjusting a potentiometer. the class of operation is set by selecting the proper value for r b shown in figure 37. r b determines the current flowing into the mode input (pin 12). for class ab operation with 15 v supplies, r b should be 150 k w . this results in a current of 95 m a. for other supply voltages, adjust the value of r b such that current remains at 95 m a. this current follows the formula: i mode = ( v cc 0.7 v ) r b the factor of 0.7 v arises from the fact that the dc bias on pin 12 is a diode drop above ground. output drive the ssm2018t is buffered by an internal op amp to provide a low impedance output. this output is capable of driving to within 1.2 v of either rail at 1% distortion for a 100 k w load. (note: this 100 k w load is in parallel with the feedback resistor of 18 k w , so the effective load is 15.3 k w .) for better than 0.01% distortion, the output should remain about 3.5 v away from either rail as shown in figure 3. as the graph of output swing versus load resistance shows (figure 10), to maintain less than 1% distortion, the output current should be limited to approximately 1.3 ma. if higher current drive is required, then the output should be buffered with a high quality op amp such as the op176 or ad797. the internal amplifiers are compensated for unity gain stability and are capable of driving a capacitive load up to 4700 pf. larger capacitive loads should be isolated from the output of the ssm2018t by the use of a 50 w series resistor. upgrading ssm2018 sockets the ssm2018t easily replaces the ssm2018 in the basic vca configuration. the parts are pin for pin compatible allowing di- rect replacement. at the same time, the trimming potentiom- eters for symmetry and offset should be removed, as shown in figure 41. upgrading to the ssm2018t immediately saves the expense of the potentiometers and the time in production of trimming for minimum distortion and control feedthrough. 18k w 50pf v+ v out 47pf nc 1? 1k w 3k w v v+ 1? 18k w 1? 18k w r b : 150k w for class ab nc = no connect r b v control v in+ v in 1 2 3 4 5 6 7 8 16 15 14 13 12 10 9 ssm2018t 11 470k w 500k w 100k w 10m w offset trim v+ v symmetry trim remove for ssm2018t figure 41. upgrading ssm2018 sockets if the ssm2018 is used in the ovce or vcp configuration, the ssm2018t can still directly replace it. however, the potenti- ometers cannot necessarily be removed, as explained in the ovce and vcp sections. temperature compensation of the gain constant as explained above, the gain constant has a 3500 ppm/ c tem- perature drift due to the inherent nature of the control port. over the full temperature range of C40 c to +85 c, the drift causes the gain to change by 7 db if the part is in a gain of 20 db. if the application requires that the gain constant be the same over a wide temperature range, then external temperature compensation should be employed. the simplest form of com- pensation is a temperature compensating resistor (tcr), such as the pt146 from precision resistor co. these elements are different from a standard thermistor in that they are linear over temperature to better match the linear drift of the gain constant.
rev. a C14C ssm2018t/ssm2118t such that full scale produces 80 db of attenuation. the resistor divider can be adjusted to provide other attenuation ranges. if a parallel interface is needed, then the dac8562 may be used, or for a dual dac, the ad8582. 0.1 m f +15v 18k w v in 6 dac8512 8 7 cs clr 2 1 0.1 m f 18k w 50pf 47pf v out 150k w +15v ?5v 0.1 m f +5v c con 1 m f r6 825 w r7 1k w 0v v c +2.24v 5 ld 3 sclk 4 sdi 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssm2018t nc nc nc nc nc = no connect figure 44. 12-bit dac controls the vca gain supply considerations and single supply operation the ssm2018t and ssm2118t have a wide operating supply range. many of the graphs in this data sheet show the perfor- mance of the part from 5 v to 18 v. these graphs offer typi- cal performance specifications and are a good indication of the parts capabilities. the minimum operating supply voltage is 4.5 v. below this voltage, the parts are inoperable. thus, to account for supply variations, the recommended minimum sup- ply is 5 v. the circuits in the data sheet do not show supply decoupling for simplicity; however, to ensure best performance, each supply pin should be decoupled with a 0.1 m f ceramic (or other low re- sistance and inductance type) capacitor as close to the package as possible. this minimizes the chance of supply noise feeding through the part and causing excessive noise in the audio fre- quency range. the ssm2018t and ssm2118t can be operated in single sup- ply mode as long as the circuit is properly biased. figure 45 shows the proper configuration, which includes an amplifier to create a false ground node midway between the supplies. a high quality, wide bandwidth audio amplifier such as the op176 or ad797 should be used to ensure a very low impedance ground over the full audio frequency range. the minimum op- erating supply for the ssm2018 is 5 v, which gives a mini- mum single supply of +10 v and ground. the performance of the circuit with +10 v is identical to graphs that show operation of the ssm2018t with 5 v supplies. 1? 2k w v c (pin 11) ssm2018t or ssm2118t 1k w * 3500ppm/ c 1k w * 3500ppm/ c control voltage *precision resistor co. 10601 75 th st. north largo, fl 34647 (813) 541-5771 figure 42. two tcrs compensate for temperature drift of gain constant +15v ?5v r3 10k w 50pf r4 1k w r5 9k w r1 10k w op176 r2 10k w 1k w * 3500ppm/ c v c (pin 11) ssm2018t or ssm2118t control voltage figure 43. current source allows temperature compen- sation with one tcr one of the resistors in the divider to the control port can be sub- stituted with an appropriately chosen tcr to compensate the ssm2018t or the ssm2118t as shown in figure 42. because the resistor divider effectively cuts the temperature coefficient in half, two tcrs must be used. the combined drift of the two is 7000 ppm/ c, given an effective drift for to the control voltage of C3500 ppm/ c. of course, a single tcr with the appropriate coefficient can be used. the 3500 ppm parts were chosen be- cause they are a standard item and do not need to be special ordered. in many applications, an op amp is used to drive the control voltage. if this is the case, it may be more economical to use the op amp and a single tcr for temperature compensation. the op amp is configured as a howland current source as shown in figure 43. the current then flows through a single tcr to create the control voltage. because the resistor divider is not present, the temp coefficient is equivalent to the tcrs coef- ficient. using this technique, the drift was reduced from C3500 ppm/ c to C150 ppm/ c, which results in a total com- pensated gain shift of 0.4 db over the full temperature range at a gain of 20 db. digital control of the gain a common method of controlling the gain of a vca is to use a digital-to-analog converter to set the control voltage. figure 44 shows a 12-bit dac, the dac8512, controlling the ssm2018t (or ssm2118t). the dac8512 is a complete 12-bit converter in an 8-pin package. it includes an on board reference and a output amplifier to produce an output voltage from 0 v to +4.095 v, which is 1 mv/bit. since the voltage is always posi- tive, this circuit only provides attenuation. the resistor divider on the output of the dac8512 is set to scale the output voltage
rev. a C15C ssm2018t/ssm2118t v+ 1 m f r b 18k v+ 18k v in+ 1 m f 18k v in 47pf 1 m f 50pf 1k v control 3k v out 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 ssm2018t v+ op176 100k 100k v+ 10 m f figure 45. single supply operation of ssm2018t operational voltage controlled element the ssm2018t has considerable flexibility beyond the basic vca circuit utilized throughout this data sheet. the name operational voltage controlled element comes from the fact that the part behaves much like an operational amplifier with a second voltage controlled output. the symbol for the ovce connected as a unity gain follower/vca is shown in figure 46. the voltage output labeled v 1Cg is fed back to the inverting in- put just as for an op amps feedback. the v g output is ampli- fied or attenuated depending upon the control voltage. because the ovce works just like an op amp, the feedback could just as easily have included resistors to add gain, or a filter network to add frequency shaping. the full circuit for the ovce is shown in figure 47. notice that the amplifier whose output (pin 16) was originally connected to v minus is now the output for feed- back. as mentioned before, because the ssm2018t is trimmed for the basic vca configuration, potentiometers are needed for the ovce configuration to ensure the best thd and control feedthrough performance. if a symmetry trim is to be performed, it should precede the control feedthrough trim and be done as follows: 1. apply a 1 khz sine wave of +10 dbu to the input, with the control voltage set for unity gain. 2. adjust the symmetry trim potentiometer to minimize distor- tion of the output signal. next the control feedthrough trim is done as follows: 1. ground the input signal port and apply a 60 hz sine wave to the control port. the sine wave should have its high and low peaks correspond to the highest gain to be used in the application and 30 db of attenuation, respectively. for ex- ample, a range of +20 db gain to 30 db attenuation requires that the sine wave amplitude ranges between C560 mv and +840 mv on pin 11. 2. adjust the control feedthrough potentiometer to null the sig- nal seen at the output. v in v c v g v 1 g figure 46. ovce follower/vca connection 18k w 50pf 470k w 500k w v+ 100k w 10m w control feedthrough trim v+ v v 1? v g inputs 220pf nc v 1? 1k w 3k w v control r b : 30k w for class a 150k w for class ab nc = no connect symmetry trim v+ r b 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssm2018t 18k w 50pf figure 47. ovce application circuit
rev. a C16C ssm2018t/ssm2118t printed in u.s.a. c1937C5C7/94 outline dimensions dimensions shown in inches and (mm). 16-pin plastic dip (n-16) package pin 1 0.280 (7.11) 0.240 (6.10) 9 16 18 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.840 (21.33) 0.745 (18.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-pin soic (r-16) package pin 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 16 9 8 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.1043 (2.65) 0.0926 (2.35) 0.4133 (10.50) 0.3977 (10.00) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.0125 (0.32) 0.0091 (0.23) voltage controlled panner an interesting circuit that is built with the ovce building block is a voltage controlled panner. figure 48 shows the feedback connection for the circuit. notice that the average of both out- puts is fed back to the input. thus, the average must be equal to the input voltage. when the control voltage is set for gain at v g , this causes v 1-g to attenuate (to keep the average the same). on the other hand, when v g is attenuated, v 1-g is amplified. the result is that the control voltage causes the input to pan from one output to the other. the following expressions show how this circuit works mathematically: v g = 2 k v in and v i g = 2(1 k ) v in where k varies between 0 and 1 as the control voltage is changed from full attenuation to full gain respectively. when v c = 0, then k = 0.5 and v g = v 1-g = v in . again, trimming is required for best performance. pin 9 should be grounded. this is possible because the feedback is constant and the adaptive network is not needed. the vcp is the only application shown in this data sheet where pin 9 is grounded. v in v c v g v 1 g 18k w 18k w figure 48. basic vcp connection

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